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应各位读者要求，小编最近按照Innovus流程顺序整理出数字IC后端项目中常用的命令汇总。限于篇幅，这次只更新到powerplan阶段。有了这份Innovus常用命令汇总，学习数字IC后端从此不再迷路！如果大家觉得这个专题还不错，想继续看数字IC后端实现powerplan之后的内容，欢迎在文末留言区留下“数字后端”四个字。
一 设计导入
1）打开Innovus数据
source maia_cpu.enc (restoreDesign maia_cpu.enc.dat maia_cpu)
2）开启&关闭图形界面
Win &win off (win是window的缩写)
3）设置cpu数量
setMultiCpuUsage -localCpu 16 （16个cpu core）
4）执行设计导入加载设计
Init_design
5）设计导入结果之时序库物理库检查
checkDesign -physicalLibrary -timingLibrary -noHtml -outfile check_design.rpt
6）设计导入结果之netlist质量检查
CheckDesign -netlist
7）设置历史命令显示
History keep 1000000
8）创建PVT时序库
create_library_set -name lib_ss_125 -timing " /pdk/TSMCHOME/digital/Front_End/timing_power_noise/ECSM/tcbn12ffcllbwp6t16p96cpd_120a/tcbn12ffcllbwp6t16p96cpdssgnp0p72v125c_hm_ecsm.lib \ /pdk/TSMCHOME/digital/Front_End/timing_power_noise/ECSM/tcbn12ffcllbwp6t16p96cpdlvt_120a/tcbn12ffcllbwp6t16p96cpdlvtssgnp0p72v125c_hm_ecsm.lib \ /pdk/TSMCHOME/sram_t12/1prf/ts5n12ffcllulvta1024x20m8swbsho_130c/CCS/ts5n12ffcllulvta1024x20m8swbsho_130c_ssgnp0p72v125c.lib \ /pdk/TSMCHOME/sram_t12/1prf/ts5n12ffcllulvta1024x32m8swbsho_130c/CCS/ts5n12ffcllulvta1024x32m8swbsho_130c_ssgnp0p72v125c.lib \ /pdk/TSMCHOME/sram_t12/1prf/ts5n12ffcllulvta128x108m2swbsho_130c/CCS/ts5n12ffcllulvta128x108m2swbsho_130c_ssgnp0p72v125c.lib /pdk/TSMCHOME/sram_t12/shdspsbsram/ts1n12ffcllsblvtd2048x64m8swbsho_130b/CCS/ts1n12ffcllsblvtd2048x64m8swbsho_130b_ssgnp0p72v125c.lib " -aocv "/pdk/TSMCHOME/digital/Front_End/SBOCV/ECSM/tcbn12ffcllbwp6t16p96cpd_120a/ssgnp0p72v125c/clock_p_data_p/tcbn12ffcllbwp6t16p96cpdssgnp0p72v125c_setup_P_P_ecsm.aocvm /pdk/TSMCHOME/digital/Front_End/SBOCV/ECSM/tcbn12ffcllbwp6t16p96cpdlvt_120a//ssgnp0p72v125c/clock_p_data_p/tcbn12ffcllbwp6t16p96cpdlvtssgnp0p72v125c_setup_P_P_ecsm.aocvm "
9）创建RC Corner
create_rc_corner -name rcworst \ -qx_tech_file {/pdk/TSMCHOME/tech_t12/QRC/rcworst/Tech/rcworst_CCworst_T/qrcTechFile} \ -preRoute_cap 1.073 \ -preRoute_res 1.173 \ -preRoute_clkcap 1.080 \ -preRoute_clkres 1.079 \ -postRoute_cap {1.0 1.032 } \ -postRoute_res {1.0 1.029 } \ -postRoute_xcap {1.0 0.946 } \ -postRoute_clkcap {0.0 1.042 } \ -postRoute_clkres {0.0 0.986 } \ -T 125
10）创建Constraint Mode
create_constraint_mode -name func -sdc_files {…/input/maia_cpu.func.sdc}
11）创建延时Delay Corner
create_delay_corner -name corner_rcmax_ss_125 -library_set {lib_ss_125} -rc_corner {rcworst}
12）创建setup和hold分析的View
create_analysis_view -name func_rcmax_ss_125 -constraint_mode {func} -delay_corner {corner_rcmax_ss_125}
13）指定工具分析setup和hold的View
set_analysis_view -setup {func_rcmax_ss_125} -hold {func_rcmin_ff_m40}
14）检查设计Netlist是否unique
checkUnique (CUI: check_unique)
15）保存设计数据
saveDesign …/db/floorplan.enc
16） 退出Innovus
exit 1
二 Floorplan
1）设置Floorplan尺寸
floorPlan -site core6T -s 1250 1100.016 2.4 2.4 2.4 2.4 （其中core6T为TSMC 12nm 6Track cell对应的site）
2）创建多边形Floorplan
set block_boundary {{1079.392 769.584} {873.817 769.584} {873.817 1108.512} {0 1108.512} {0 0} {1079.392 0}}
create_rectilinear_block_boundary -block_name maia_cpu -boundary $block_boundary -core2die 2.4
setObjFPlanBoxList Cell maia_cpu {{0.00000 940 1254.81600 1104.81600} {0.00000 0.00000 1019.35550 940}}
Low Power Design |各Power Domain多边形形状设置，不同高度Row创建，effective PD等
3）摆放io port
editPin -fixOverlap 1 -unit MICRON -spreadDirection clockwise -edge 2 -layer 6 -spreadType start -spacing 0.16 -start 200 200 -pin [get_object_name [all_outputs ]]
4）读入设计def
defIn mem.def
5）添加placement blockage
createPlaceBlockage -box $bbox -name Placement_blockage -type hard
6）创建site row
CreateRow
7）切割Row
cutRow
8）删除Row
DeleteRow
9）Floorplan相关object snap对齐
snapFPlan
10）添加io port buffer
attachIOBuffer -in $in_clk_buf_name -out $out_clk_buf_name -status fixed -suffix $clkname_prefix -selNetFile $sel_net_file_name
80万+年薪的数字后端简历到底长什么样？
11）添加endcap cell
addEndCap
12）添加tapcell
addWellTap -cell TAPCELLBWP6T16P96CPD -cellInterval 48 -checkerBoard -check_channel -prefix WELLTAP -inRowOffset 4.032
13）Verify tapcell distance
verifyWellTap -cell “BOUNDARY_NTAPBWP6T16P96CPD BOUNDARY_PTAPBWP6T16P96CPD_VPP TAPCELLBWP6T16P96CPD” -rule 48
三 Powerplan
1）创建PG逻辑连接
globalNetConnect VDD_CORE -type pgpin -pin {VDD} -inst * -override
globalNetConnect VDD_CORE -type tiehi -pin {VDD} -inst * -override
2）定义特殊通孔VIA类型
add_via_definition -name via12_usrdefine -via_rule VIAGEN12_RECT -row_col {1 10} -cut_size {0.13 0.05} -bottom_enclosure {0.02 0.02} -top_enclosure {0.08 0.08} -cut_spacing {0.21 0.13}
add_via_definition -name via23_usrdefine -via_rule VIAGEN23_RECT -row_col {1 10} -cut_size {0.13 0.05} -bottom_enclosure {0.02 0.02} -top_enclosure {0.08 0.08} -cut_spacing {0.21 0.13}
https://alidocs.dingtalk.com/i/nodes/jkB7yl4ZK3vV6P2rdqya8PMX2O6oxqw0?doc_type=wiki_doc&utm_medium=main_vertical&utm_scene=team_space&utm_source=search# 「分享一个powerplan对绕线资源影响的案例（面试可以分享这个过程）」
3）指定特殊VIA类型打孔
setViaGenMode -viarule_preference { via12_usrdefine via23_usrdefine via34_usrdefine via45_usrdefine via56_usrdefine via67_usrdefine via78_usrdefine via89_usrdefine}
4）为指定区域添加power stripe
addStripe -area $channel1 \ -number_of_sets 1 -nets “VDD_CORE VSS” -width 4 -spacing 1 -layer M8 \ -direction vertical \ -start_offset 2 \ -uda power_m8_channel1
5）添加电源环Power Ring
addRing -nets {VDD_PPS VSS} -type core_rings -follow io -layer {top METAL3 bottom METAL3 left METAL4 right METAL4} -width {top 2 bottom 2 left 2 right 2} -spacing {top 1 bottom 1 left 1 right 1} -offset {top 0 bottom 0 left 0 right 0} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid None
6）创建power rail电源轨道
sroute -connect { corePin } \ -layerChangeRange { M1(1) M8(8) } \ -corePinTarget { none } \ -allowJogging 1 \ -crossoverViaLayerRange { M1(1) M8(8) } \ -nets { VDD_CORE VSS } \ -allowLayerChange 1 \ -targetViaLayerRange { M1(1) M8(8) } \ -uda power_rail_M1
7）PG Pin连接性检查
verifyConnectivity -type special -noAntenna -noWeakConnect -noUnroutedNet -error 1000 -warning 50 -net VDD_CORE
verifyConnectivity -type special -noAntenna -noWeakConnect -noUnroutedNet -error 1000 -warning 50 -net VSS
8）DRC检查
verify_drc
9）PG Short检查
verify_PG_short -no_routing_blkg
10）打孔
editPowerVia -top_layer M2 -bottom_layer M1 -delete_vias true
11)修复Via的drc
fixVia -cutSpacing -shape FOLLOWPIN -layer {VIA1}
